1. Field of the Invention
The present invention relates to an analog-to-digital conversion method and device for converting an input voltage into numerical data.
2. Description of the Related Art
In the past, analog-to-digital (A/D) conversion devices have been used to convert an input voltage into numerical data by utilizing a pulse delay circuit that has a plurality of delay units, each of which is realized with a gate circuit, connected in tandem. One analog-to-digital conversion device is disclosed in, for example, Japanese Unexamined Patent Publication Application No. 5-259907.
This type of analog-to-digital conversion device is configured as shown in, for example, FIG. 8A or FIG. 8B.
To begin with, the analog-to-digital conversion device shown in FIG. 8A has a pulse delay circuit 10 and a latch and encoder 12. The pulse delay circuit 10 has a plurality of delay units 2 connected in tandem. The delay unit 2 delays an input pulse Pin by a predetermined delay time and outputs it. The latch and encoder 12 detects (latches) the position of the input pulse Pin in the pulse delay circuit 10, to which the input pulse Pin has reached, at the leading edge (or trailing edge) of a sampling signal CKS that is received from outside. The latch and encoder 12 then converts the result of detection into digital data DT, which consists of a predetermined number of bits and represents how many delay units succeed the delay unit 2 through which the input pulse Pin has just passed, and transfers the digital data.
The delay units 2 constituting the pulse delay circuit 10 are realized with gate circuits each including an inverter or the like. An input voltage Vin that is an object of analog-to-digital conversion is applied to each delay unit 2 via a buffer 14 or the like.
Consequently, the delay time given by the delay unit 2 is proportional to the level of the input voltage Vin. Eventually, the number of delay units 2 through which the input pulse Pin has passed within the pulse delay circuit 10 during a sampling cycle TS of the sampling signal CKS is proportional to the level of the input voltage Vin.
For example, FIG. 9A graphically shows changes in outputs of the delay units 2(1), 2(2), 2(3), etc. occurring when the input pulse Pin is transferred within the pulse delay circuit 10. As is apparent from the drawing, when the input voltage Vin is high, the delay time given to the input pulse Pin by each delay unit 2 is short. Therefore, the number of delay units 2 through which the input pulse Pin passes within the pulse delay circuit 10 during a sampling cycle TS increases (in the drawing, ten delay units starting with the first delay unit 2(1) and ending with the tenth delay unit 2(10)). When the input voltage Vin is low, the delay time given to the input pulse Pin by each delay unit 2 is long. Therefore, the number of delay units 2 through which the input pulse Pin passes within the pulse delay circuit 10 during a sampling cycle TS decreases (in the drawing, seven delay units starting with the first delay unit 2(1) and ending with the seventh delay unit 2(7)).
Consequently, the output (digital data DT) of the latch and encoder 12 varies depending on the level of the input voltage Vin. The digital data DT is numerical data resulting from analog-to-digital conversion of the input voltage Vin.
In the analog-to-digital conversion device shown in FIG. 8A, the transfer rate SP at which the input pulse Pin is transferred within the pulse delay circuit 10 varies, as shown in FIG. 9B, in proportion to the input voltage Vin that is applied as a driving voltage to each delay unit 2. The latch and encoder 12 is therefore used to measure the number of delay units 2, through which the input pulse Pin has passed, at intervals of a predetermined sampling cycle TS. Thus, the input voltage Vin is converted into numerical data (digital data DT).
The analog-to-digital conversion device shown in FIG. 8B is different from the analog-to-digital conversion device shown in FIG. 8A in the point that the first delay unit 2 included in the pulse delay circuit 10 is realized with an AND gate one of whose input terminals serves as an activation terminal. The other input terminal of the first delay unit 2 is connected to the output terminal of the last delay unit 2, whereby all the delay units 2 are concatenated annularly. Thus, the pulse delay circuit 10 is constructed as a ring delay line (RDL) having the input pulse Pin circulated through it. Furthermore, a counter 16 and a latching circuit 18 are included in the analog-to-digital conversion device. The counter 16 counts the number of times by which the input pulse Pin is circulated within the pulse delay circuit 10. The latching circuit 18 latches the count value produced by the counter 16 at the leading edge (or trailing edge) of the sampling signal CKS.
In the analog-to-digital conversion device having the foregoing circuitry, digital data provided by the latch and encoder 12 is digital data DT whose low-order bits a are assigned to the level of the input voltage Vin and whose high-order bits b are assigned to the count value transferred from the latching circuit 18. Compared with the analog-to-digital conversion device shown in FIG. 8A, the number of delay units 2 constituting the pulse delay circuit 10 can be decreased.
As shown in FIG. 8C, in the foregoing conventional analog-to-digital conversion devices, the number of delay units through which the input pulse Pin has passed is numerically calculated at intervals of a certain sampling cycle TS. Thus, the input voltage Vin is converted into the numerical data (digital data DT). The resolution in analog-to-digital conversion is determined with the time (delay time) required for the input pulse Pin to pass through each delay unit 2.
The delay time to be given by the delay unit 2 is determined with the properties of the gate circuits realizing the delay units. In order to improve the resolution in analog-to-digital conversion performed by the conventional analog-to-digital conversion devices, the unit delay time to be given by each gate circuit must be shortened through sophistication of the gate circuit manufacturing technology. This poses a problem in that improvement of the resolution in analog-to-digital conversion is limited by the gate circuit manufacturing technology.
FIG. 10 is an explanatory diagram showing the relationship among a resolution for a voltage that is a digitized value, a delay time given by each delay unit 2 (unit delay time Td), and a rule for use in manufacturing a microstructural CMOS inverter (CMOS design rule). Herein, the delay unit 2 included in the analog-to-digital conversion device shown in FIG. 8A is realized with two CMOS inverters, and the analog-to-digital conversion device acts at the frequency of the sampling signal CKS (sampling frequency) of 10 kHz and at the ambient temperature of 25° C. In order to improve the resolution for the voltage that is a digitized value produced by the conventional A/D conversion devices, the CMOS design rule must be made smaller so that the unit delay time Td to be given by the delay unit 2 will be shorter. For this purpose, there is no way other than a wait for sophistication of the microstructure manufacturing technology required for manufacturing a gate circuit that realizes the delay unit 2.
Moreover, in the conventional A/D conversion devices, the sampling cycle TS should be shortened in order to increase an analog-to-digital conversion rate. However, shortening the sampling cycle TS leads to a decrease in the number of bits constituting digital data produced in proportion to the input voltage Vin, and eventually to a reduction in a resolution. Therefore, the analog-to-digital conversion devices cannot be adapted to an application requiring high-speed analog-to-digital conversion that yields a desired resolution (for example, 10 bits and 1 MHz) because of the insufficient conversion rate.
On the other hand, in the conventional analog-to-digital conversion devices, the delay time to be given by each of the delay units 2 constituting the pulse delay circuit not only varies depending on the input voltage Vin but also varies depending on the environment for use such as ambient temperature. Namely, although the input voltage Vin remains unchanged, when the temperature is low, the delay time given by each delay unit 2 becomes shorter. Consequently, the transfer rate SP of the input pulse Pin within the pulse delay circuit 10 assumes a value, as shown in FIG. 9B, attained when the input voltage Vin is high. In contrast, when the temperature is high, the delay time given by each delay unit 2 becomes longer. Therefore, the transfer rate SP of the input pulse Pin within the pulse delay circuit 10 assumes a value, as shown in FIG. 9B, attained when the input voltage Vin is low.
In efforts to solve the foregoing problems, the technologies disclosed in, for example, Japanese Unexamined Patent Publication Applications Nos. 7-154256, 5-37378, 11-44585, and 11-64135 are utilized. Namely, both the input voltage Vin that is an object of analog-to-digital conversion and a constant reference voltage are digitized, a ratio of the resultant data items is calculated, and a variation of the digitized value of the input voltage Vin deriving from an environmental change is canceled. According to this countermeasure, the analog-to-digital conversion of the input voltage Vin and the analog-to-digital conversion of the reference voltage must be performed sequentially by switching inputs of the analog-to-digital conversion device. It therefore takes too much time to work out a desired digitized value. Moreover, a switching circuit for switching the inputs of the analog-to-digital conversion device and a circuit for canceling a variation must be included additionally. This poses a problem in that the configuration of the A/D conversion device becomes complex and the cost thereof increases.